1. Field of the Invention
The present invention relates to a semiconductor device and, more specifically, to a semiconductor device including a bipolar transistor.
2. Description of the Background Art
A method of manufacturing a conventional semiconductor device including a bipolar transistor will now be described. First, as shown in FIG. 15, an Nxe2x88x92 epitaxial layer 102 is formed on a semiconductor substrate 101. A field oxide film 103 is formed on Nxe2x88x92 epitaxial layer 102.
A polysilicon film (not shown) is formed on semiconductor substrate 101 by CVD (Chemical Vapor Deposition) covering an element formation region of semiconductor substrate 101 separated by field oxide film 103.
Thereafter, a prescribed impurity to form an external base diffusion layer is implanted into the polysilicon film as shown in FIG. 16. An external base leading electrode 104 is formed by prescribed etching of the polysilicon film.
As shown in FIG. 17, a silicon oxide film 105 is formed on semiconductor substrate 101 by CVD covering external base leading electrode 104. Then, as shown in FIG. 18, a resist pattern 106 is formed on silicon oxide film 105.
An opening 125 to be a base region is formed by anisotropic etching of silicon oxide film 105 and external base leading electrode 104 using resist pattern 106 as a mask. During this step, a surface portion of Nxe2x88x92 epitaxial layer 102 is etched to some extent.
As shown in FIG. 19, by an oxidation, impurity implanted into external base leading electrode 104 is diffused from a surface of Nxe2x88x92 epitaxial layer 102 to the inside, and an external base diffusion layer 108 is formed. In this step, a relatively thin silicon oxide film 107 is formed on a region such as an exposed surface region of Nxe2x88x92 epitaxial layer 102.
Thereafter, as shown in FIG. 20, a prescribed impurity to form an intrinsic base diffusion layer is implanted into Nxe2x88x92 epitaxial layer 102 as an intrinsic base implantation. Then, a silicon oxide film (not shown) is formed on silicon oxide film 105 with the CVD method. By performing anisotropic etching of the silicon oxide film and exposing the surface of Nxe2x88x92 epitaxial layer 102, a sidewall oxide film 109 is formed as shown in FIG. 21.
As shown in FIG. 22, a polysilicon film 110 (or an amorphous silicon film) is formed on silicon oxide film 105 with the CVD method. Then, a prescribed impurity to form an emitter diffusion layer is implanted into polysilicon film 110 as an emitter implantation.
As shown in FIG. 23, an emitter leading electrode 110a is formed by a prescribed patterning of polysilicon film 110. An interlayer silicon oxide film 111 is formed with the CVD method so as to cover emitter leading electrode 110a. 
Thereafter, the impurity implanted as the intrinsic base implantation is diffused by a heat treatment to form an intrinsic base diffusion layer 112. The impurity implanted as the emitter implantation is diffused to form an emitter diffusion layer 113.
As shown in FIG. 24, prescribed contact holes 111a-111c are respectively formed by prescribed etching of interlayer silicon oxide film 111. Then, an aluminum film (not shown) is formed with sputtering, for example, to fill contact holes 111a-111c. 
As shown in FIG. 25, a collector electrode 116, a base electrode 114 and an emitter electrode 115 are respectively formed by a prescribed patterning of the aluminum film. As a result, a semiconductor device including a bipolar transistor T is formed.
The conventional semiconductor device has, however, problems as follows. Intrinsic base diffusion layer 112 is formed in the step shown in FIG. 23 by a heat treatment of the prescribed impurity which was implanted into Nxe2x88x92 epitaxial layer 102 in the step shown in FIG. 20.
To ensure an electrical connection between intrinsic base diffusion layer 112 formed as such and external base diffusion layer 108, it is necessary to diffuse the impurity for external base diffusion layer 108 to a deeper region of semiconductor substrate 101, and to make the etched amount (removed amount) of the surface portion of Nxe2x88x92 epitaxial layer 102 as small as possible when opening 125 for the base region is formed.
In the step shown in FIG. 19, on the other hand, when the impurity for external base diffusion layer 108 is to be diffused to a deeper region of Nxe2x88x92 epitaxial layer 102 by a heat treatment while making small the removed amount of the surface portion of Nxe2x88x92 epitaxial layer 102 located on the bottom of opening 125, the impurity will also be diffused to a lateral (horizontal) direction.
That is, the impurity will be diffused toward a portion of Nxe2x88x92 epitaxial layer 102 located near a center of the bottom of opening 125, as well as toward a portion of Nxe2x88x92 epitaxial layer 102 located directly below field oxide film 103.
Particularly, when the impurity is diffused toward the portion of Nxe2x88x92 epitaxial layer 102 located near the center of the bottom of opening 125, a distance L between external base diffusion layer 108 and emitter diffusion layer 113 becomes smaller as shown, for example, in FIG. 23. As a result, breakdown voltage between the emitter and base decreases.
In addition, an injection efficiency of the emitter decreases in a portion around emitter diffusion layer 113, and a current gain hFE decreases when the distance L becomes smaller.
Furthermore, an impurity concentration in intrinsic base diffusion layer 112 around emitter diffusion layer 113 is affected by the distance L between external base diffusion layer 108 and emitter diffusion layer 113 depending on the size of the bipolar transistor. Consequently, an injection efficiency of electrons and the current gain hFE vary around emitter diffusion layer 113.
The present invention is made to solve the above-described problems. An object of the present invention is to provide a semiconductor device which suppresses decrease in breakdown voltage between an emitter and a base and suppresses decrease and variation of current gain hFE.
A semiconductor device according to the present invention includes an element formation region formed on a main surface of a semiconductor substrate of a first conductivity type, an insulator film, an opening, a first conductive material portion, a first impurity region of a first conductivity type, a second conductive material portion, a second impurity region of a second conductivity type, and a third impurity region of a second conductivity type. The element formation region formed on the main surface of the semiconductor substrate is separated by an element isolation insulator film. The insulator film is formed on the semiconductor substrate so as to cover the element formation region. The opening is formed in the insulator film and the element formation region, and has a sidewall and a bottom exposing a region of the semiconductor substrate located approximately on the center portion of the element formation region. The first conductive material portion is formed between the semiconductor substrate and the insulator film, and extends from a side of the element isolation insulator film to the opening and is exposed at the sidewall of the opening. The first impurity region of the first conductivity type is formed on a surface portion of the semiconductor substrate exposed at the bottom of the opening. The second conductive material portion is electrically connected to the first impurity region. The second impurity region of the second conductivity type is formed on the semiconductor substrate so as to enclose the first impurity region from side and bottom, and to include the surface portion of the semiconductor substrate exposed at the bottom of the opening. The third impurity region of the second conductivity type is formed on a surface portion of the semiconductor substrate within the element formation region, extends from a side of the element isolation insulator film to the opening and is exposed at the sidewall of the opening, and is electrically connected with the second impurity region. The surface portion of the semiconductor substrate within the element formation region is inclined substantially upward from the side of the element isolation insulator film to the sidewall of the opening.
In a bipolar transistor having the first impurity region as an emitter, the second and third impurity regions as a base, and the semiconductor substrate of the first conductivity type as a collector according to this structure, because the surface portion of the semiconductor substrate is inclined substantially upward from the side of the element isolation insulator film to the sidewall of the opening, a sufficient distance between the portion of the third impurity region located on the side of the sidewall of the opening and the first impurity region located on the bottom of the opening is ensured, as compared with a conventional semiconductor device without such inclination when the third impurity region is formed by diffusing the impurity of the second conductivity type implanted into the first conductive material portion to the portion of the semiconductor substrate within the element formation region. As a result, sufficient breakdown voltage of the first impurity region (emitter) and the third impurity region (base) can be ensured. In addition, when the second impurity region is formed by diffusing the impurity of the second conductivity type, which impurity is introduced to the surface portion of the semiconductor substrate exposed at the bottom of the opening, toward the third impurity region formed by diffusing the impurity of the second conductivity type, because the surface portion of the semiconductor substrate wherein the third impurity region is formed is inclined substantially upward from the side of the element isolation insulator film to the sidewall of the opening, it is ensured that the impurity diffusing laterally to form the second impurity region reaches the third impurity region, and the second and third impurity regions are electrically connected easily to each other.
In addition, it is preferable that the portion of the sidewall of the opening exposing the third impurity region is tapered to be wider upward.
With this, because the length along the sidewall from the surface (upper surface) position of the semiconductor substrate to the bottom of the opening in the portion of the semiconductor substrate exposed at the sidewall of the opening becomes longer than that in the opening without tapered sidewall, the impurity introduced from the upper surface of the semiconductor substrate to form the third impurity region is less diffused to the portion of the semiconductor substrate located on the bottom of the opening. As a result, the decrease in the breakdown voltage between the first and third impurity regions can certainly be prevented. At the same time, because the impurity concentration of the second impurity region (intrinsic base diffusion layer) located around the first impurity region is not affected by the distance between the third impurity region (external base diffusion layer) and the first impurity region depending on the size of the bipolar transistor, variation in the injection efficiency of electrons in the portion around the first impurity region decreases, and variation in current gain hFE can be suppressed.
Furthermore, as the first and third impurity regions get close to each other if the impurity region to form the third impurity region is diffused to the region of the semiconductor substrate located on the bottom of the opening, it is preferable that a depth of a lower end of the third impurity region on the sidewall of the opening is substantially equal to or smaller than that of the bottom of the opening, to substantially prevent the first and third impurity regions from getting close to each other.
With this, the variation in the injection efficiency of electrons in the portion around the first impurity region can surely be reduced, and the variation in current gain hFE can certainly be suppressed.